1. Field of the Invention
The present invention relates generally to a method for identification and test generation for primitive faults, and more particularly pertains to identification and test generation for primitive faults in multi-level or two-level netlists combinational circuits.
Increasing circuit operating frequencies and demands for low cost and high quality require that the temporal correctness of a circuit can be guaranteed. For high performance circuits with aggressive timing requirements, small process variations can lead to failures at the design clock rate. These defects can stay undetected after at-speed or stuck-at-fault testing. To detect them, the design has to be subjected to delay testing.
2. Discussion of the Prior Art
A path delay fault model is frequently used in delay testing for detecting distributed manufacturing defects. In this model a circuit is considered faulty if the propagation delay of any of its paths exceeds the clock period. A path in a combinational circuit is an ordered set of gates g.sub.0, . . . , g.sub.n where g.sub.0 and g.sub.n are a primary input and output, respectively, and gate g.sub.i is an input to gate g.sub.i+1 (0.ltoreq.i.ltoreq.n-1). A delay defect on a path can be observed by propagating a transition through the path. This requires application of a two-vector test, V=&lt;v.sub.1, v.sub.2 .ltoreq.. Therefore, a path delay fault specification consists of a physical path and a transition that will be applied at the beginning of the path.
Research on path delay fault testing shows that there are several different path delay fault classes. Defects on robustly (R) testable paths are guaranteed to be detected regardless of delays on the other signals in the circuit. Defects on non-robustly (NR) testable paths can be detected if transitions on certain signals outside the target path are not late. Functional sensitizable (FS) path delay faults may degrade the circuit performance if several path delay faults simultaneously occur. Functional redundant (FR) paths can never determine the performance of the circuit and they do not have to be tested. Paths that can affect the performance of the circuit (robust, non-robust and functional sensitizable paths) are together called functional irredundant (FIRR) paths. FIG. 1 illustrates the path delay fault classification system.
Testing strategies exist for robust and non-robust path delay faults. However, usually only a small portion of functional irredundant path delay faults can be tested under the robust and non-robust criteria. On the other hand, the set of functional sensitizable faults can be very large. Functional sensitizable paths are false paths if no other path delay faults simultaneously exist in the circuit. However, if some other path delay fault is present at the same time, functional sensitizable faults can become true paths and can determine the performance of the circuit. Typically, a number of different tests have to be applied to guarantee that a given FS path is delay fault-free. This is because a given FS path can belong to many different groups of paths that can together affect the performance of the circuit. An FS path is thoroughly tested by some test set T if after applying T it can be guaranteed that the target path is delay fault free. In the publication by W. Ke and P. R. Menon, Delay-Verifiability of Combinational Circuits Based on Primitive Faults, Proceedings of IEEE International Conference on Computer Design, pages 86-90, October 1994, a special class of multiple path delay faults called primitive faults has been introduced. It is known that testing all primitive faults would result in a thorough testing of all FS paths.
Testing of FS paths has been addressed by several research groups. However, no practical method has been proposed for testing of these faults in circuits described as multi-level netlists. This is because (1) testing of FS paths requires developing testing strategies for some multiple fault conditions and (2) identification of the conditions under which the fault on some FS path can be detected is a complex task.
In delay testing, the inability to generate tests for some multiple path delay faults can lead to a poor delay test quality. This is unlike stuck-at fault testing wherein tests developed under single fault assumption can offer high fault coverage. For example, consider circuit s1269 from the ISCAS 89 set of benchmarks. Fully scanned and mapped into 2-input gates this circuit has a total of 79,138 paths. The number of all functional irredundant paths is 18,506. Only 5.4% of the functional irredundant paths are robustly or non-robustly testable while 94.6% are functional sensitizable. FIG. 2 shows the number of paths with delay longer than the corresponding path delay for (1) robustly and non-robustly testable paths (graph (a)) and (2) functional sensitizable paths (graph (b)). The delays are obtained from a timing analyzer. The longest robust or non-robust path has a delay of 43.5 ns while the longest functional sensitizable path has a delay of 105.3 ns. Therefore, the robust and non-robust test set can detect only path defects whose total size is more than twice the delay of the path. Small manufacturing defects might not result in such large delay defects. However, they can cause a small delay increase on more than one long path. In circuits like this one, such defects could be detected only be testing functional sensitizable paths.